team

Shanthi Pavan

Professor

Sc.D  degrees from Columbia University, New York in 1999

M.S   degree from Columbia University, New York in 1997

B.Tech  degree in Electronics and Communication Engg from the Indian Institute of Technology, Madras in 1995

044-2257 4437

shanthi@ee.iitm.ac.in

Personal Link

  • Shanthi Pavan obtained the B.Tech degree in Electronics and Communication Engg from the Indian Institute of Technology, Madras in 1995 and the M.S and Sc.D degrees from Columbia University, New York in 1997 and 1999 respectively. From 1997 to 2000, he was with Texas Instruments in Warren, New Jersey, where he worked on high speed analog filters and data converters. From 2000 to June 2002, he worked on microwave ICs for data communication at Bigbear Networks in Sunnyvale, California. Since July 2002, he has been with the Indian Institute of Technology-Madras, where he is now the NT Alexander Institute Chair Professor of Electrical Engineering. His research interests are in the areas of high speed analog circuit design and signal processing.
  • Dr.Pavan is the recipient of the Shanti Swarup Bhatnagar Award in Engineering Sciences (2012), IEEE Circuits and Systems Society Darlington Best Paper Award (2009), the Swarnajayanthi Fellowship (2010, from the Government of India) , the Young Faculty Recognition Award from IIT Madras (2009, for excellence in teaching) , the Technomentor Award from the India Semiconductor Association (2010) and the Young Engineer Award from the Indian National Academy of Engineering (2006). He has been the Editor-in-Chief of the IEEE Transactions on Circuits and Systems: Part I - Regular Papers (2014-2015), and earlier served on the editorial board of the IEEE Transactions on Circuits and Systems Part II - Express Briefs (2006-2007). He has served as a Distinguished Lecturer of the IEEE Solid State Circuits Society, and on the technical program committee of the International Solid-State Circuits Conference (ISSCC). He is a fellow of the Indian National Academy of Engineering (INAE) , the Indian National Science Academy (INSA), and the Institute of Electrical and Electronic Engineers (IEEE).

  • Analog, Mixed-Signal and RF VLSI Design

  • Fellow, Indian National Science Academy (2023)
  • Vasvik Award for Industrial Research, 2020
  • Wiley-IEEE Press Professional Book Award for Understanding Delta-Sigma Data Converters, 2nd Edition, 2020.
  • Distinguished Lecturer of the IEEE Circuits and Systems Society, 2018-2019.
  • Fellow, IEEE (Class of 2018), for contributions to Delta-Sigma modulators and analog filters.
  • Distinguished Lecturer of the IEEE Solid State Circuits Society, 2015-16.
  • Mid-career Research and Development Award, IIT Madras, 2016.
  • Editor-in-Chief, IEEE Transactions on Circuits and Systems : Regular Papers, 2014-2015.
  • Deputy Editor-in-Chief, IEEE Transactions on Circuits and Systems : Regular Papers, 2012-2013.
  • Shanti Swarup Bhatnagar Award in Engineering Sciences, 2012.
  • Fellow, Indian National Academy of Engineering.
  • Techno mentor Award from the India Semiconductor Association.
  • Swarna jayanthi Fellowship from the Department of Science and Technology, Govt of India.
  • Young Faculty Recognition Award from IIT Madras.
  • Darlington Best Paper Award from the IEEE Circuits and Systems Society.
  • Young Engineer Award from the Indian National Academy of Engineering.

Journals

  • S Pavan, T Halder and A Kannan, Continuous-time Incremental Delta-Sigma Modulators with FIR Feedback IEEE Transactions on Circuits and Systems: Regular Papers , to appear.
  • S Manivannan and S Pavan, A 65nm CMOS Continuous-Time Pipeline ADC achieving 70dB SNDR in 100MHz Bandwidth IEEE Solid-State Circuits Letters , May 2021.
  • A Baluni and S Pavan, Analysis and Design of a 20 MHz Bandwidth Continuous-Time Delta-Sigma Modulator With Time-Interleaved Virtual-Ground-Switched FIR Feedback IEEE Journal of Solid-State Circuits , March 2021.
  • S Pavan and H Shibata, Continuous-time Pipelined Analog-to-Digital Converters: A Mini-Tutorial IEEE Transactions on Circuits and Systems: Express Briefs , March 2021.
  • S Manivannan and S Pavan, Improved Continuous-Time Delta-Sigma Modulators with Embedded Active Filtering IEEE Transactions on Circuits and Systems: Regular Papers , October 2020.
  • S Billa, S Dixit and S Pavan, Analysis and Design of an Audio Continuous-Time 1-X FIR-MASH Delta-Sigma Modulator IEEE Journal of Solid State Circuits , October 2020.
  • R Theertham, P Koottala, S Billa and S Pavan, Design Techniques for High-Resolution Continuous-Time Delta-Sigma Converters With Low In-Band Noise Spectral Density IEEE Journal of Solid State Circuits , September 2020.
  • S Javvaji, V Singhal, V Menezes, R Chauhan and S Pavan, Analysis and Design of a Multi-Step Bias-Flip Rectifier for Piezoelectric Energy Harvesting IEEE Journal of Solid State Circuits , September 2019.
  • R Theertham and S Pavan, Improved Offline Calibration of DAC Mismatch Errors in Delta Sigma Data Converters , IEEE Transactions on Circuits and Systems: Express Briefs, October 2019.
  • R Theertham and S Pavan, Unified Analysis, Modeling, and Simulation of Chopping Artifacts in Continuous-Time Delta-Sigma Modulators , IEEE Transactions on Circuits and Systems: Regular Papers, August 2019.

Conference Proceedings

  • K Singh and S Pavan, A 14 bit dual channel incremental continuous-time Delta Sigma modulator for multiplexed data acquisition, IEEE International Conference on VLSI Design}, pages 1--5 IEEE, 2016.
  • S Billa, A Sukumaran, and S Pavan, A 280uW, 24kHz BW, 98,5dB SNDR, chopped single-bit CTDSM achieving less than 10 Hz 1/f noise corner without chopping artifacts, IEEE International Solid State Circuits Conference (ISSCC), pages 1--2 IEEE, 2016.
  • A Sukumaran and S Pavan, A continuous-time Delta Sigma modulator with 91dB dynamic range in a 2 MHz signal bandwidth using a dual switched-capacitor return-to-zero DAC, Proceedings of the European Solid-State Circuits Conference (ESSCIRC), pages 217--220 IEEE, 2015.
  • N Rajesh and S Pavan, Programmable analog pulse shaping for ultra-wideband applications, IEEE International Symposium on Circuits and Systems (ISCAS), pages 461--464 IEEE, 2015.
  • N Rajesh and S Pavan, Improved characterization of differential multi-GHz integrated amplifiers and filters, Proceedings of the IEEE International Microwave Symposium, pages 461--464 IEEE, 2015.
  • S Krishnan and S Pavan, A 10 Gbps eye opening monitor in 65nm CMOS, IEEE International Symposium on Circuits and Systems (ISCAS), pages 3028--3031 IEEE, 2015.
  • R Rajan and S Pavan, A 5mW CT Delta Sigma ADC with embedded second order active filter and VGA achieving 82dB dynamic range in 2MHz bandwidth, 2014 IEEE International Solid-State Circuits Conference, Digest of Technical Papers (ISSCC), pages 156--158, 2014.
  • S Pavan, Efficient estimation of the signal and noise transfer functions of a continuous time Delta Sigma modulator, Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), Melbourne, pages 1--4, 2014
  • M Veeramani, N Ratchagar, E Bhattacharya, S Pavan, S Prakash, and A Chadha, Compact silicon biosensor for the clinical range estimation of blood serum triglyceride, IEEE SENSORS , pages 1--4 IEEE, 2013.
  • A Sukumaran and S Pavan,A 280uW audio continuous-time Delta Sigma modulator with 103 dB DR and 102 dB A-Weighted SNR, Proceedings of the Asian Solid State Circuits Conference, Singapore , pages 1--4, 2013.

Patents

  • Shanthi Pavan, Integrated circuit implementation for power and area efficient adaptive equalization, US 7,142,596, Nov 28, 2006; jointly assigned to Indian Institute of Technology Madras and Vitesse Semiconductor, California.
  • John S Wang, Sudeep Bhoja, Shanthi Pavan, Hai Tao, Method and apparatus for improved high-speed adaptive equalization, US 7,003,228, Feb 21, 2006.
  • Shanthi Pavan et al,Mobility Compensation in MOS Integrated Circuits, US 6,822,505, 23 Nov 2004.
  • Shanthi Pavan et al, Method and System for Compensation of Low-frequency Photodiode Current in a Transimpedance Amplifier, US 6,552,615, 22 Apr 2003.
  • Shanthi Pavan et al, Programmable Analog Tapped Delay Line Filter Having Cascaded Differential Delay Cells, US 6,545,567, 8 Apr 2003.
  • Shanthi Pavan, Fixed Transconductance Bias Apparatus, US 6,400,185, 4 Jun 2002.
  • Shanthi Pavan et al, Fast Acting Polarity Detector, US 6,369,726, 2 Apr 2002.
  • Shanthi Pavan, Low Distortion Sample-and-Hold Circuit, US 6,323,697, 27 Nov 2001.
  • Shanthi Pavan, High Frequency Boost Technique, US 6,304,134, 16 Oct 2001.
  • Shanthi Pavan et al, Method and Apparatus for Tuning High-Q Bandpass Filters using Pulse Excitation, US 5,945,889, 31 Aug 1999.

Books Authored

  • Understanding Delta-Sigma Modulators, 2nd Edition, Wiley-IEEE Press
  • High Frequency Continuous Time Filters in Digital CMOS Processes authored by Shanthi Pavan , Yannis Tsividis.
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